module img_data(
    input               clk               ,   // 48MHz
    input               rst_n             ,
    input       [7:0]   img_data_i        ,
    input               img_href_i        ,   // image data valid enable
    input               img_vsync_i       ,   // vertical sync signal
    input               init_done         ,   // 初始化结束后开始发送数据
    input               ddr_init_done     ,
    output reg  [7:0]   fifo_wr_data      ,
    output reg          fifo_wr_en          
);

// ------------------< reg define >-----------------------
// 对接收到的数据缓存打拍
reg [7:0] img_data, img_data_i_d1, img_data_i_d2;
reg [3:0] frame_cnt;
reg img_href, img_href_i_d1, img_href_i_d2;
reg img_vsync, img_vsync_i_d1, img_vsync_i_d2;
// 取沿
reg img_vsync_d1, img_href_d1;
// 开始接收数据的信号
reg data_in_en;
reg first_row;
// ------------------< wire define >----------------------
wire neg_img_href;
wire frame_init_done;
//              main code
// 标志第一行帧
assign neg_img_vsync = (~img_vsync) & img_vsync_d1; 
assign neg_img_href = (~img_href) & img_href_d1; 
// 先打拍，防止亚稳态
always @(posedge clk or negedge rst_n) begin 
    if(~rst_n)begin
        img_data_i_d1  <= 8'd0;
        img_data_i_d2  <= 8'd0;
        img_href_i_d1  <= 1'd0;
        img_href_i_d2  <= 1'd0;
        img_vsync_i_d1 <= 1'd0;
        img_vsync_i_d2 <= 1'd0;
        img_data       <= 8'd0;
        img_href       <= 1'd0;
        img_vsync      <= 1'd0;
    end
    else begin
        img_data_i_d1 <= img_data_i;
        img_data_i_d2 <= img_data_i_d1;
        img_data <= img_data_i_d2;

        img_href_i_d1 <= img_href_i;
        img_href_i_d2 <= img_href_i_d1;
        img_href <= img_href_i_d2;

        img_vsync_i_d1 <= img_vsync_i;
        img_vsync_i_d2 <= img_vsync_i_d1;
        img_vsync <= img_vsync_i_d2;
    end
end

// 取沿
always @(posedge clk or negedge rst_n) begin 
    if(~rst_n)begin
        img_vsync_d1 <= 1'd0;
        img_href_d1 <= 1'd0;
    end
    else begin
        img_vsync_d1 <= img_vsync;
        img_href_d1 <= img_href;
    end
end

// 第一行数据标志信号
always @(posedge clk or negedge rst_n) begin 
    if(~rst_n)begin
        first_row <= 1'd0;
    end
    else if(neg_img_vsync)
        first_row <= 1'd1;
    else if(neg_img_href)
        first_row <= 1'd0;
    else
        first_row <= first_row;
end

// frame_cnt
always @(posedge clk or negedge rst_n) begin 
    if(~rst_n)
        frame_cnt <= 4'd0;
    else if(frame_cnt == 4'd11)
        frame_cnt <= frame_cnt;
    else if(neg_img_vsync)
        frame_cnt <= frame_cnt + 4'd1;
    else
        frame_cnt <= frame_cnt;
end

// frame_init_done
assign frame_init_done = (frame_cnt == 4'd11) ? 1'd1 :1'd0;
// 等待摄像头和ddr初始化结束，同时数据为帧的第一行时开始接收数据
always @(posedge clk or negedge rst_n) begin 
    if(~rst_n)
        data_in_en <= 1'd0;
    else
        data_in_en <= (init_done && ddr_init_done && first_row && frame_init_done) ? 1'd1 : data_in_en;
end

// 初始化结束后开始将数据写入fifo
always @(posedge clk or negedge rst_n) begin
    if(~rst_n)begin
        fifo_wr_en <= 1'd0;
        fifo_wr_data <= 8'd0;
    end
    else begin
        if(data_in_en)begin
            if(img_href)begin                
                fifo_wr_en <= 1'd1;
                fifo_wr_data <= img_data;
            end
            else begin
                fifo_wr_en <= 1'd0;
                fifo_wr_data <= 8'd0;
            end   
        end
        else ;
    end
end
endmodule